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Semiconductor Engineering
United States
Приєднався 27 чер 2011
System-Level Design, Low-Power/High-Performance Engineering and Semiconductor Manufacturing & Design are focused on deep technology and business issues in semiconductor design, implementation, integration and manufacturing.
Making Electronics More Efficient
Projections about the amount of energy required for AI in data centers and other electronic devices are putting a spotlight on more efficient electronics. But making chips and systems more efficient is an enormous challenge. It used to be as simple as turning down the voltage or moving to the next process node, but those approaches are no longer yielding the same kinds of benefits as in the past. Andy Heinig, head of department for efficient electronics at Fraunhofer IIS/EAS, talks with Semiconductor Engineering about the impact of disaggregation and chiplets, where the pitfalls are with partitioning and modeling, and what's missing out of the design flow today to enable better efficiency.
Переглядів: 362
Відео
Software-Defined Vehicles
Переглядів 3339 днів тому
Speed is everything when it comes to designing automotive electronics, but not in the usual way. In the past, product cycles often lasted five to seven years, from initial design to implementation inside of vehicles. That no longer works as vehicles adopt more electronics to replace mechanical functionality, and as competition heats up over the latest features and nearly instantaneous over-the-...
Changes In Formal Verification
Переглядів 56822 дні тому
For the better part of two decades, formal verification was considered too difficult to use in many designs and too slow for anything but narrow bug hunting. Much has changed recently. Ashish Darbari, CEO of Axiomise, talks with Semiconductor Engineering about why formal is now essential for finding deadlocks, security holes, and Xprop issues in mission-critical, safety-critical, and AI designs...
Promises And Pitfalls Of SoC Restructuring
Переглядів 586Місяць тому
As chips become more complex and increasingly heterogeneous, it's becoming more difficult to keep track of different methodologies, tools, and blend data from different sources to create a chip. Tim Schneider, staff application engineer at Arteris, talks with Semiconductor Engineering about why IP-XACT has become so critical, why it took so long to gain a solid foothold in chip design, and how ...
Making Adaptive Test Work Better
Переглядів 420Місяць тому
One of the big challenges for IC test is making sense of mountains of data, a direct result of more features being packed onto a single die, or multiple chiplets being assembled into an advanced package. Collecting all that data through various agents and building models on the tester no longer makes sense for a couple reasons - there is too much data, and there are multiple customers using the...
MCU Changes At The Edge
Переглядів 9652 місяці тому
Microcontrollers are becoming a key platform for processing machine learning at the edge due to two significant changes. First, they now can include multiple cores, including some for high performance and others for low power, as well as other specialized processing elements such as neural network accelerators. Second, machine learning algorithms have been pruned to the point where inferencing ...
Electromigration And IR Drop At Advanced Nodes
Переглядів 8852 місяці тому
Manufacturing chips at 3nm and below is a challenge, but it's only part of the problem. Designing chips that can be manufactured and will actually work is potentially an even bigger problem. There is more data to sift through for place-and-route, less margin to pad a design, and there are more physical effects to contend with as transistors get taller, density increases, and chips age. Jeff Wil...
Adapting To Evolving IC Requirements
Переглядів 4452 місяці тому
As chip designs become increasingly heterogeneous and domain-specific, packing a device with one-size-fits-all chips or chiplets doesn't make sense. The key is rightsizing different components based on real workloads, so they don't waste power when there is too little utilization of logic, and so they don't struggle to complete tasks because they are undersized. Jayson Bethurem, vice president ...
Sensor Fusion Challenges In Automotive
Переглядів 6323 місяці тому
The number of sensors in automobiles is growing rapidly alongside new safety features and increasing levels of autonomy. The challenge is integrating them in a way that makes sense, because these sensors are optimized for different types of data, sometimes with different resolution requirements even for the same type of data, and frequently with very different latency, power consumption, and re...
Overlay Optimization In Advanced IC Substrates
Переглядів 8163 місяці тому
Overlay is becoming a significant problem in the manufacturing of semiconductors, especially in the world of advanced packaging substrates - think panels - the larger the area, the greater the potential for distortion due to warpage. Solving this issue requires more accurate models, better communication through feed forward/feed back throughout the flow, and real-time analytics that are baked i...
Secure Movement Of Data In Test
Переглядів 3243 місяці тому
Historically, test data flowed out of the tester and was loaded into a file. But with heterogeneous integration, including chiplets and IP from multiple vendors, test data is now being streamed across the manufacturing floor where it can be used to make real-time decisions. Eli Roth, product manager for smart manufacturing at Teradyne, talks with Semiconductor Engineering about challenges in da...
Challenges With Chiplets And Power Delivery
Переглядів 1,5 тис.3 місяці тому
Chiplets hold the potential to deliver the same power, performance, and area benefits as an SoC, but with many more features and options that are possible on a reticle-constrained die. If chiplets live up to the hype, they will deliver what is essentially mass customization, democratizing and speeding the delivery of complex chips across a broad array of markets. Today, the focus has been on di...
Challenges In RISC-V Verification
Переглядів 1,1 тис.4 місяці тому
Designing a single-core RISC-V processor is relatively easy, but verifying it and debugging it is a different story. And it all becomes more complicated when multiple cores are involved, and when those cores need to be cache-coherent. Ashish Darbari, CEO of Axiomise, talks with Semiconductor Engineering about using assertions and formal verification technology to find bugs and prove coherency i...
Cache Coherency In Heterogeneous Systems
Переглядів 9004 місяці тому
Until recently, coherency was something normally associated with DRAM. But as chip designs become increasingly heterogeneous, incorporating more and different types of compute elements, it becomes harder to maintain coherency in that data without taking a significant hit on performance and power. The basic problem is that not all compute elements fetch and share data at the same speed, and syst...
Rethinking Chip Economics
Переглядів 1,2 тис.4 місяці тому
As process nodes shrink, so does the selection of chips developed at those nodes. Consumers demand more features and functionality, but that carries a high price tag in terms of both complexity and real dollars. In addition, because costs are skyrocketing, there is growing pressure for those chips to remain reliable and up-to-date for longer periods of time. Jayson Bethurem, vice president of m...
Awesome video.
thanks
too much fast
I feel like there’s about 99% than what’s discussed here, but this was still a bit helpful.
Thank you so very much Steven 🎉 its so very informative. Numbers and spécifications you provide are so valuable, thanks again!!! 🙆
Thank you Mr.Gideon for your informative video!!
This serves as formal notification of the successful receipt of the BTC transaction.
Fascinating. I wonder if there's any memory degradation over the eFPGA reprogramming cycles?
This is great to watch because my PhD thesis work is on cryogenic MRAM for embedded quantum computing hardware. Thanks for the video :D
Lot of hand waving. Such is the beast the cloud is. Very fluffy and vague vapor. This was five years ago. Things have moved a lot in these five years. I hop you do another video on where we are now on this issue.
Where can I get a tsmc28nm HBM phy?
Great video!! Thanks!
Thx for sharing Doctor Fried. Do we use "Mahalanobis Distance", etc. to optimize "Process Window Optimization"?
Fantastic, but l have aquestion How l use inkjetprinting for printing sensors
What about interface considerations? Do you design for specific interfaces?
I have an solid state analog transmitter of 85 Kw (LARCAN) working uninterrupted for almost 35 years. I am really impressed about how these MOSFET(MRF151G) are still working at maximum RF power without any kind of maintenance.
A GPU made with HMB memory for working memory and GDDR6 memory for a second teir of working memory and background memory. a graphics card like this would be so fast.
Hello there, Analog layout engineer here and I’m watching this in 2024😂, fuck the future robots who gonna replace VLSI engineers,
@2:25 T0 - T1 ? -> since we are talking about Delta on arrival times, should it not be negating, rather than adding? Thanks much for the video !
Density is becoming an issue with reliability. Too much density causes bit flips
Not enough videos and documentation explaining these techniques . Thank you for uploading
Great. AI Clusters seems to be limited by GPU memory and rack bandwidth, so an increasing fraction of silicone and power will go into communication. So great to hear that optics can save a lot of power.
interesting. SO moving from tripling the whole computer , to tripling the critical parts in the IC and leveraging development for faults tolerance from automotive chips.
I was taught to be almost paranoid with ESDs when handling chips and boards, but hearing how much engineering goes into the indented discharge paths goes, explain why people being more casual with their handling still are able to build working devices.
Insightful
Superb
Thank you for your input. This video helped me understand where I need to focus my effort as a backend engineer for timing related issues.
Next video why chips age
Great stuff gentlemen. From a custom fiber cable assembly house perspective, this is very interesting
Very informative!
Great that we get this for free! Have seen some really interesting ideas in this space
How to add this SDC to the simulation?
Super interesting and informative video, thanks!
Very interesting considerations to think about. Many thanks 🙏
I will sleep less ignorant today.
Thanks for visiting us Ed, and looking forward to many future discussions!
This looks like cut tree and partitioning
Great insight 👍
Wow! What about SMEE?
Excellent Video. Shed light on a few things I was wondering about. Well explained.
Thank you for this wonderful explanation
thanks for you guys's effort to this great video.
Does the fact that high NA EUV is anamorphic mean on axis has higher resolution than the other?
Very interesting technology explanation - awesome
thanks for posting this
So we gotta update the routing algorithms for curvy linear design
Interesting 😀
Wow!
Great video. Helped a lot !!
great video, thx